Symptom: Vivado freezes or takes forever to synthesize. Fix: You wrote a for-loop in Verilog that runs 10,000 times. Remember: Hardware runs in parallel. Loops are fine for testbenches, but in real RTL, loops mean you are copying the same circuit 10,000 times. Use counters instead.

So, your professor just dropped the bomb: "For this lab, you will be using Xilinx Vivado."

Instead of re-adding files every time, type: add_files -norecurse ./src/top.v

Instead of clicking "Run Synthesis" ten times, type: launch_runs synth_1 -jobs 4

From "Where is the compile button?" to "Look, my LED blinked!" – Your roadmap to mastering FPGA design. Introduction: The "Blinking LED" Rite of Passage